library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity ALU is
    port(CS: in bit_vector (1 downto 0);
         A, B: in unsigned (15 downto 0);
         Result: out unsigned (15 downto 0));
end ALU;

architecture structure of ALU is
begin
    process(A,B,CS)
    begin
        if    CS = "00" then Result <= A + B;   -- add
        elsif CS = "01" then Result <= A and B;   -- and
        elsif CS = "10" then Result <= A xor B;  -- xor
        elsif CS = "11" then Result <= A;   -- passa
        end if;
    end process;
end structure;
